ICS650-01B
System Peripheral Clock Source
MDS 650-01B A
1
Revision 041499
Printed 11/15/00
Integrated Circuit Systems 525 Race Street San Jose CA95126 (408) 295-9800tel (408) 295-9818fax
The ICS650-01B is a low cost, low jitter, high
performance clock synthesizer for system
peripheral applications. Using analog/digital
Phase-Locked Loop (PLL) techniques, the device
accepts a parallel resonant 14.31818 MHz crystal
input to produce up to eight output clocks. The
device provides clocks for PCI, SCSI, Fast
Ethernet, Ethernet, and AC97. The user can select
from multiple interface frequencies, and also one
of three AC97 audio frequencies. The OE pin puts
all outputs into a high impedance state for board
level testing. All frequencies are generated with less
than one ppm error, meeting the demands of SCSI
and Ethernet clocking.
The ICS650 can be mask customized to produce
any frequencies from 1 to 150 MHz.
Block Diagram
Description
Features
Packaged in 20 pin tiny SSOP (QSOP)
Operating VDD of 3.3V or 5V
Less than one ppm synthesis error in all clocks
Inexpensive 14.31818 MHz crystal or clock input
Provides Ethernet and Fast Ethernet clocks
Provides SCSI clocks
Provides PCI clocks
Selectable AC97 audio clock
Selectable interface clock
OE pin tri-states the outputs for testing
Selectable frequencies on three clocks
Duty cycle of 40/60
Advanced, low power CMOS process
Crystal
Oscillator
Clock
Synthesis
Circuitry
Output
Buffer
B Clock 1
Output
Buffer
Audio Clock
Processor Clocks
(Fast Ethernet,
SCSI, PCI )
Output
Buffer
2
PSEL1:0
14.31818 MHz
crystal
X1
X2
14.31818 MHz
Output
Buffer
4
ASEL
BSEL
B Clock 2
Output
Buffer
Output Enable (all outputs)
ICS650-01B
System Peripheral Clock Source
MDS 650-01B A
2
Revision 041499
Printed 11/15/00
Integrated Circuit Systems 525 Race Street San Jose CA95126 (408) 295-9800tel (408) 295-9818fax
Pin #
Name
Type
Description
1
BSEL
I
BCLK1 and BCLK2 Select pin. Determines frequency of B clocks per table above.
2
X2
XO
Crystal connection. Connect to parallel mode 14.31818 MHz crystal. Leave open for clock.
3
X1
XI
Crystal connection. Connect to parallel mode 14.31818 MHz crystal, or clock.
4
VDD
P
Connect to VDD. Must be same value as other VDD. Decouple with pin 6.
5
GND
P
Connect to ground.
6
GND
P
Connect to ground.
7
BCLK1
O
BCLK1 output. Determined by BSEL pin per table above.
8
BCLK2
O
BCLK2 output. Determined by BSEL pin per table above. Only clock active if PSEL1, 0=1.
9
ACLK
O
AC97 Audio clock output per table above.
10
PCLK4
O
PCLK output number 4 per table above.
11
OE
I
Output Enable. Tri-states all outputs when low.
12
PCLK1
O
PCLK output number 1 per table above.
13
14.318M
O
14.31818 MHz buffered reference clock output.
14
GND
P
Connect to ground.
15
ASEL
I
ACLK Select pin. Determines frequency of Audio clock per table above.
16
VDD
P
Connect to VDD. Must be same value as other VDD. Decouple with pin 14.
17
PCLK3
O
PCLK output number 3 per table above.
18
PCLK2
O
PCLK output number 2 per table above.
19
PSEL0
I
Processor Select pin #0. Determines frequencies on PCLKs 1-4 per table above.
20
PSEL1
I
Processor Select pin #1. Determines frequencies on PCLKs 1-4 per table above.
Pin Descriptions
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection
1
16
2
3
4
15
14
13
VDD
ACLK
X2
VDD
20 pin (150 mil) SSOP
5
6
7
8
12
11
10
9
PCLK4
PSEL0
X1
BSEL
PCLK2
PSEL1
PCLK3
PCLK1
OE
BCLK2
BCLK1
18
17
19
20
GND
GND
14.318M
GND
ASEL
PSEL1
PSEL0
PCLK1 PCLK2,3
PCLK4
0
0
25.00
50.00
18.75
0
M
TEST
TEST
TEST
0
1
TEST
TEST
TEST
M
0
40.00
80.00
20.00
M
M
33.3334
66.6667
25.00
M
1
20.00
40.00
25.00
1
0
20.00
33.3334
25.00
1
M
20.00
66.6667
25.00
1
1
Stops low all cloocks except BCL
LK2.
Processor Clock (MHz)
BSEL
BCLK1
BCLK2
0
3.688
4.917
M
50
25
1
80
40
Audio Clock (MHz)
B Clocks (MHz)
0 = connect directly to ground, 1 = connect directly
to VDD, M=leave unconnected (floating)
Pin Assignment
ASEL
ACLK
0
49.152
M
24.576
1
12.288
ICS650-01B
System Peripheral Clock Source
MDS 650-01B A
3
Revision 041499
Printed 11/15/00
Integrated Circuit Systems 525 Race Street San Jose CA95126 (408) 295-9800tel (408) 295-9818fax
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (n
note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
C
Soldering Temperature
Max of 10 seconds
260
C
Storage temperature
-65
150
C
DC CHARACTERISTICS (VDD = 3.3V
V or 5V unless noted))
Operating Voltage, VDD
3.0
5.5
V
Input High Voltage, VIH
Select inputs, OE
2
V
Input Low Voltage, VIL
Select inputs, OE
0.8
V
Output High Voltage, VOH
VDD=3.3V, IOH=-8mA
2.4
V
Output Low Voltage, VOL
VDD=3.3V, IOL=8mA
0.4
V
Output High Voltage, VOH, VDD = 3.3 or 5V
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD, at 5V
No Load, note 2
50
mA
Operating Supply Current, IDD, at 3.3V
No Load, note 2
25
mA
Short Circuit Current, VDD = 3.3
Each output
50
mA
Input Capacitance
Except X1
7
pF
AC CHARACTERISTICS (VDD = 3.3V
V or 5V unless noted)
Input Crystal or Clock Frequency
14.31818
M H z
Output Clocks Accuracy (synthesis error)
All clocks
1
ppm
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At VDD/2
40
50
60
%
One Sigma Jitter
Except ACLK
75
ps
One Sigma Jitter
ACLK
170
ps
Absolute Clock Period Jitter
PCLK, UCLK, BCLK
- 500
500
ps
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest frequencies.
External Components
The ICS650 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01F should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14),
as close to the chip as possible. A series termination resistor of 33
may be used for each clock output. The
14.31818 MHz crystal must be connected as close to the chip as possible. The crystal should be a
fundamental mode, parallel resonant, 30 ppm or better (to meet the Ethernet specs). Crystal capacitors
should be connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by
the following equation, where C
L
is the crystal load capacitance: Crystal caps (pF) = (C
L
-12) x 2. So for a
crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1
and leave X2 unconnected.
ICS650-01B
System Peripheral Clock Source
MDS 650-01B A
4
Revision 041499
Printed 11/15/00
Integrated Circuit Systems 525 Race Street San Jose CA95126 (408) 295-9800tel (408) 295-9818fax
Package Outline and Package Dimensions
Ordering Information
Part/Order Number
Marking
Package
Shipping
Temperature
ICS650R-01
ICS650R-01
20 pin SSOP
Tubes
0 to 70 C
ICS650R-01T
ICS650R-01
20 pin SSOP
Tape and Reel
0 to 70 C
ICS650R-01I
ICS650R01I
20 pin SSOP
Tubes
-40 to 85 C
ICS650R-01IT
ICS650R01I
20 pin SSOP
Tape and Reel
-40 to 85 C
20 pin SSOP
Millimeters
Symbol
Min
Max
A
1.55
1.73
b
0.203
0.305
c
0.190
0.254
D
8.560
8.740
E
3.810
4.000
H
5.840
6.200
e
0.635 B
BSC
h
0.410
L
0.016
0.035
Q
0.127
0.250
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
b
D
E
H
e
Q
c
h x 45
A
L
PDF 
ZIP